1. Field of the Invention
This invention is related to the field of integrated circuit design tools and, more particularly, to annotating stress parameters onto schematics in a hierarchical design.
2. Description of the Related Art
At current semiconductor fabrication process levels (e.g. 32 nanometer (nm) and below), the transistors in an integrated circuit “chip” are strongly influenced by the structure of the transistors, the nearby circuitry, circuit density, and the location of the transistors on the chip. The effects can be modeled by applying stress parameters to each transistor instance (e.g. a threshold voltage (VT) modifier and a mobility modifier). Unfortunately, the design flow only supports stress parameter annotation as part of a flattening process. That is, even though the design files, such as schematics, can have a hierarchical nature in which a higher-level design file instantiates a lower level design file (potentially multiple times), the hierarchy is first flattened into one larger database. The larger, flat database matches the layout of the chip, allowing the physical location (and corresponding stress parameters) to be identified.
For large designs, the latency to perform the stress parameter annotation is unacceptably long, leading designers to avoid it at higher levels in the hierarchy. Additionally, the flattening destroys the hierarchies, which makes it impossible to skip or black-box individual hierarchies. The underlying circuitry may have already been processed and need not be repeated. Furthermore, it may be desirable to skip some circuit hierarchies, which is not possible in the flat process.